Logic coll_r, coll_l // screen collision flags Logic ball_dx_prev // direction in previous tick (for shot counting)
Logic ball_dx, ball_dy // direction: 0 is right/down Logic ball_spy // vertical speed (pixels/frame) Logic ball_spx // horizontal speed (pixels/frame)
Logic ball_x, ball_y // position (origin at top left) Logic frame // high for one clock tick at the start of vertical blankingĪlways_comb frame = (sy = V_RES & sx = 0) Localparam V_RES = 480 // vertical screen resolution Localparam H_RES = 640 // horizontal screen resolution screen dimensions (must match display_inst) Localparam PAD_SPY = 3 // vertical paddle speed Localparam PAD_OFFS = 32 // paddle distance from edge of screen in pixels Localparam PAD_WIDTH = 10 // paddle width in pixels Localparam PAD_HEIGHT = 48 // paddle height in pixels Localparam BALL_ISPY = 3 // initial vertical ball speed Localparam BALL_ISPX = 5 // initial horizontal ball speed Localparam BALL_SIZE = 8 // ball size in pixels Localparam SPEEDUP = 5 // speed up ball after this many shots (max 16) Localparam WIN = 4 // score needed to win a game (max 9) Output logic sdl_de, // data enable (low in blanking interval) Output logic sdl_sy, // vertical SDL position Output logic sdl_sx, // horizontal SDL position Input wire logic btn_fire, // fire button Module top_pong #( parameter CORDW = 10) ( // coordinate width Have a glance over it, then scroll down to learn how the different parts of the design work. Here’s the whole game as a Verilator simulation. You can edit the simulation keyboard controls in main_pong.cpp. Try the design out on your board or in simulation see the README or Sim README for build instructions. I’ve chosen FPGA design over authenticity, but you’re welcome to change the design however you like (it’s open source): This design is not based on the detail of the original Pong gameplay. If you’d like to learn more about the early history of Atari, including Pong, I recommend the book Racing the Beam by Nick Montfort and Ian Bogost. You can also watch Pong gameplay on YouTube.
PONG GAME CODE IN VHDL PDF
The Pong Story explains the history of Atari Pong and includes a detailed PDF on the design: Atari Pong E Circuit Analysis & Lawn Tennis. Originally an arcade cabinet, it was quickly adapted for play at home with a television. Pong may not have been the first computer game, but it has an excellent claim to being the first to break into public consciousness on release in 1972. Photo by Sergey Galyonkin under Creative Commons Attribution-Share Alike licence. See requirements from Beginning FPGA Graphics for more details. I include everything you need for the iCEBreaker with 12-Bit DVI Pmod, Digilent Arty A7-35T with Pmod VGA, and Verilator Simulation with SDL. You should be to run these designs on any recent FPGA board. My hardware designs are open source, and my blog is advert free. I love FPGAs and want to help more people discover and use them in their projects. If you like what I do, consider sponsoring me on GitHub. Animated Shapes - animation and double-buffering.2D Shapes - filled shapes and simple pictures.Lines and Triangles - drawing lines and triangles.Life on Screen - Conway’s Game of Life in logic.Framebuffers - bitmap graphics featuring Michelangelo’s David.Hardware Sprites - fast, colourful graphics for games.Display Signals - revisit display signals and meet colour palettes.Pong (this post) - recreate the classic arcade on an FPGA.Racing the Beam - simple demos with minimal logic.Beginning FPGA Graphics - video signals and basic graphics.Get in touch: GitHub Issues, 1BitSquared Discord, (Mastodon), (Twitter) New to the series? Start with Beginning FPGA Graphics. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. This post was completely revised in April 2022. Last time, we raced the beam this time, we’ll recreate the classic arcade Pong and play against our FPGA.
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